1. Field of the Invention
The invention relates to improvements in sense-write circuits for random access memories.
2. Brief Description of the Prior Art
A variety of sense-write circuits for ECL (emitter-coupled logic) memory arrays are known in the art. One example of such a circuit is described in U.S. Pat. No. 3,919,566, and typical decoding circuitry for an ECL memory array is described in U.S. Pat. No. 3,914,620, both by Millhollan, et al and both assigned to the present assignee. Both of the above patents are incorporated herein by reference. The known ECL sense-write circuits utilize two differential stages, one for establishing a sense voltage on a bit sense line of the memory array, and the other operating to establish the Write-Data and Write-Data voltages on the bit-sense lines during write operations. Separate current sources are required for each of the differential stages. The topology in integrated circuit layout for multiple differential stages does not optimize use of chip area. Needlessly complex interface circuitry between the differential stages and the bit-sense lines in the memory array is required.